IC 74173 DATASHEET PDF

datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.

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During normal operation of the device, the outputs of the D flip—flops appear at these pins. The 3-state outputs allow the device to be used in bus organized systems. When both Data Enable Controls are low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input.

When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state. When either M or N or both is are high the output is disabled to the high-impedance state.

During 3—state operation, these outputs assume a high— impedance state. When either or both of these controls are high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs. Output Enable Controls are high, the Q outputs of the device.

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74173 PDF Datasheet浏览和下载

The data outputs change state on the positive going edge of the clock. Active—low Data Enable Control inputs. If dtaasheet of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs. The 3-state outputs allow the. A high level on this pin resets all.

The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The outputs are placed in the 3-stage mode when either of the. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state.

The four D type Flip-Flops operate synchronously from a common clock.

Datasheet, PDF – Alldatasheet

Output Enable Control inputs. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock.

Data on these pins, when enabled by the. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in datashdet state.

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The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. When either M or N or both is are high datasheft output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. When both controls are low, the device outputs display the data in the flip—flops.

(PDF) 74173 Datasheet download

When either or both of the. Data—Enable Controls, are entered into the flip—flops on the. During 3—state operation, these outputs assume a high—.

Clearing is enabled by taking the clear input to a logic high level. Home – IC Supply – Link.

– Quad D-type flip-flop; positive-edge trigger; 3-state – ChipDB

During normal operation of the. Enable Controls are low, data at the D inputs are loaded into. When both controls are.

Home – IC Supply – Link. Clearing is enabled by taking the clear input to a logic.